1. Field of the Invention
The invention generally relates to voltage peak measurement apparatus and methods and in particular to such voltage peak measurement techniques that may be used in units or subunits of communication systems such as WLAN (Wireless Local Area Network) systems.
2. Description of the Related Art
A wireless local area network is a flexible data communication system implemented as an extension to, or as an alternative for, a wired LAN. Using radio frequency (RF) or infrared technology, WLAN systems transmit and receive data over the air, minimizing the need for wired connections. Thus, WLAN systems combine data connectivity with user mobility. Most WLAN systems use spread spectrum technology, a wide-band radio frequency technique developed for use in reliable and secure communication systems. The spread spectrum technology is designed to trade-off bandwidth efficiency for reliability, integrity and security.
One element in wireless communication systems are RF transceivers. Today, RF transceivers are often provided as integrated circuits and the realization of RF transceivers in highly integrated circuits may be a requirement for applications such as those in wireless local area networks and in the cellular telephony to achieve a very high dynamic range and a very high frequency on the one hand and a low power consumption and a reduction in the passive components on the other hand.
FIG. 1 shows a typical configuration of a conventional voltage peak measurement apparatus that detects peak values of an analog signal (Vin) and outputs digital results corresponding to the detected peak values. The peak measurement configuration of FIG. 1 comprises an analog to digital converter 100, a reference voltage source 130, a capacitor 160, a diode 190 and a reset switch 150 connected to discharge the capacitor 160.
The analog to digital converter 100 is a known device that comprises different input terminals 120, 140. A first input terminal is a peak voltage input terminal 140 that is connected to receive the peak voltage (Vpeak) of the analog signal (Vin) applied to the input terminals 170, 180 of the peak measurement configuration.
A second input terminal is a reference voltage input terminal 120. The reference voltage input terminal 120 is connected to a reference voltage source 130 to provide a reference voltage (Vref). As shown in FIG. 1, the other side of the reference voltage source 130 is connected to a common ground line that is further connected to the input terminal 180.
A further input terminal of the conventional analog to digital converter 100 is a clock terminal 110 to receive an external clock signal that may be used to synchronize internal devices of the analog to digital converter 100.
As mentioned above, the input terminal 170 of the peak measurement configuration is connected to the peak voltage input terminal 140 of the analog to digital converter 100. This connection is referred to as an input line hereafter. Between the input line and the common ground line, there are the capacitor 160 and the reset switch 150 connected in parallel thereto.
The terminal 140 receives a rectified analog voltage signal, and also the capacitor 160 receives the applied rectified analog voltage. The capacitor 160 is charged and holds a voltage corresponding to the currently applied analog voltage. This held voltage is a peak voltage of the applied analog voltage and the analog to digital converter 100 converts the held peak voltage into digital data.
The peak measurement configuration of FIG. 1 has several disadvantages. In particular, the usage of the capacitor 160 and the reset switch 150 for discharging the capacitor. 160 is disadvantageous. Referring to the signal graphs of FIG. 2, the function of the conventional peak measurement configuration of FIG. 1 will be explained in more detail and the disadvantages will be pointed out. FIG. 2 illustrates an example of an input signal received at the input terminals 170, 180 of the peak measurement configuration of FIG. 1. Further, a reset signal is illustrated that indicates when the reset switch 150 of the peak measurement configuration of FIG. 1 discharges the capacitor 160.
After the reset switch 150 is turned off, the discharged capacitor 160 is then ready to store a voltage peak of the applied input signal. The signal graphs of FIG. 2 show that the falling edge 230 of the reset signal initiates the charging of the capacitor 160. The capacitor 160 holds the first voltage peak 240 of the input signal as long as a further, higher voltage peak 250, 260 is applied, or until the capacitor 160 is discharged by the reset switch 150. Thus, the capacitor voltage represents the maximum of the input voltage (Vin) since the last reset, thus the input voltage peak.
When the capacitor 160 holds a voltage level, the connected analog to digital converter 100 generates a digital output corresponding to the held voltage level.
It is well known that each capacitor discharges due to leak currents. This process of discharging effects an error 220 that decreases the currently stored peak voltage level 260 over time. The decreased peak voltage level is delivered to the analog to digital converter 100, and the analog to digital converter 100 generates output data that does not represent the original peak voltage level of the analog voltage applied to the peak measurement configuration of FIG. 1 but the decreased level.
Assuming the capacitor of FIG. 1 receives a rectified voltage signal that is generated by an input circuit that comprises a diode and a current source for generating a bias current for keeping the diode at a given operating point in forward direction, the current source will effect a further decrease of the stored voltage level of the capacitor 160 in addition to the above-described discharging effect because the current of the current source may speed up the discharging of the capacitor 160.
A further disadvantage of the conventional configuration of FIG. 1 is the fact that discharging the capacitor 160 introduces a time dependent error. Therefore, it is necessary to balance between measurement time, discharge of the capacitor 160 and, in case of a rectified signal, the bias current of the diode for rectifying, to minimize operating point dependent errors and to provide the needed signal bandwidth.
The above-described effects are difficult to balance and decrease the available signal bandwidth. Further, the disadvantages lead to a decreased operating speed of the peak measurement configuration and result in less precision and less accuracy.
An improved voltage peak measurement apparatus, an integrated circuit chip, a WLAN receiver and an operation method are provided for performing a voltage peak measurement that may allow for high operating speed, high precision and high accuracy.
In one embodiment, there is provided a voltage peak measurement apparatus for measuring a peak value of an analog voltage. The apparatus comprises an analog to digital converter that is connected to receive an input voltage. The analog to digital converter comprises a voltage level detection unit that is adapted to detect a voltage level of the received input voltage, and a digital memory that is connected to the voltage level detection unit for receiving and storing the detected voltage level. The digital memory is adapted for updating the stored voltage level by a currently detected voltage level only if the currently detected voltage level is higher than the stored voltage level, or updating the stored voltage level by a currently detected voltage level only if the currently detected voltage level is lower than the stored voltage level. The digital memory is capable of outputting a digital code that corresponds to the stored voltage level.
In a further embodiment, an integrated circuit chip has circuitry for measuring a peak value of an analog voltage. The integrated circuit chip comprises an analog to digital converter circuit that is connected to receive an input voltage. The analog to digital converter circuit comprises a voltage level detection circuit that is adapted to detect a voltage level of the received input voltage, and a digital memory circuit that is connected to the voltage level detection circuit for receiving and storing the detected voltage level. The digital memory circuit is adapted for updating the stored voltage level by a currently detected voltage level only if the currently detected voltage level is higher than the stored voltage level, or updating the stored voltage level by a currently detected voltage level only if the currently detected voltage level is lower than the stored voltage level. The digital memory circuit is capable of outputting a digital code that corresponds to the stored voltage level.
In another embodiment, there is provided a WLAN receiver that has a voltage peak measurement device for measuring a peak value of an analog voltage. The device comprises an analog to digital converter that is connected to receive an input voltage. The analog to digital converter comprises a voltage level detection unit that is adapted to detect a voltage level of the received input voltage, and a digital memory that is connected to the voltage level detection unit for receiving and storing the detected voltage level. The digital memory is adapted for updating the stored voltage level by a currently detected voltage level only if the currently detected voltage level is higher than the stored voltage level, or updating the stored voltage level by a currently detected voltage level only if the currently detected voltage level is lower than the stored voltage level. The digital memory is capable of outputting a digital code that corresponds to the stored voltage level.
In yet another embodiment, there is provided a method of measuring a peak value of an analog voltage. The method comprises receiving an input voltage in an analog to digital converter, detecting a voltage level of the received input voltage, storing the detected voltage level in a digital memory, and outputting a digital code that corresponds to the stored voltage level. The stored voltage level is updated by a currently detected voltage level only if the currently detected voltage level is higher than the stored voltage level, or the stored voltage level is updated by a currently detected voltage level only if the currently detected voltage level is lower than the stored voltage level.